Preface: The AMD EPYC 9004 and 9005 series processors heavily demand—and absolutely dominate—the High-Performance Computing (HPC) and AI markets.

Because CPUs and GPUs have fundamentally different processing architectures, there is no single “1-to-1” equivalence. Instead, the number of AMD EPYC 9005 (Zen 5 “Turin”) processors needed to equal one NVIDIA H100 GPU depends entirely on the workload math precision you are running. Based on raw mathematical computing power (FLOPS), it takes anywhere from 3 to 400+ EPYC 9005 CPUs to match a single NVIDIA H100.

Background: The Python script shown in the infographic simulates the underlying logic behind the timing-side channel vulnerability.

By exiting early (return b”Decryption Failed”) as soon as ciphertext[i] != secret_key[i], the execution time becomes directly proportional to how many leading bytes the attacker guessed correctly.

The mechanism in this code mirrors real-world cryptographic flaws found in foundational security infrastructure, such as the TCG TPM 2.0 reference code flaws like CVE-2026-6727.

Why the Code is a Spot-On Simulation

1.             Information Leakage via Early Exit:

• A guess of XOCK fails on byte index 0 and exits immediately (minimal loop iterations).
• A guess of LOCX passes indices 0, 1, 2 and fails on index 3 (maximum loop iterations).

2.             Measurable Metric: When run over thousands of trials (as your measure_execution_time function does), the nanosecond differences accumulate. This allows an attacker to statistically deduce the key one byte at a time (e.g., if L… takes noticeably longer than A… through K…, the attacker knows the first letter is L).

The mechanism in this code mirrors real-world cryptographic flaws found in foundational security infrastructure, such as the TCG TPM 2.0 reference code flaws like CVE-2026-6727.

Vulnerability details: CVE-2026-6727 (non-AMD)  – A timing side-channel vulnerability in RSA OAEP decryption was reported in the TCG TPM 2.0 reference code that could allow a local attacker with elevated privileges to decrypt ciphertexts (import blobs, credential blobs, and session salts) encrypted to the RSA Endorsement Key or falsify TPM 2.0 Attestation Keys.

AMD has analyzed the Trusted Computing Group’s report and believes Firmware TPMs on AMD platforms are impacted by this vulnerability.

Remedy: AMD recommends updating to the Platform Initialization (PI) firmware version.

Official announcement: Please refer to the link for details – https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7064.html

Preface: AMD EPYC processors include RAPL (Running Average Power Limit) functionality, which provides a standardized cross-vendor interface for enterprise data centers. Enterprise Linux ecosystems rely heavily on built-in diagnostic and orchestration frameworks. By exposing counters through the RAPL standard via the Linux PowerCap and perf subsystems, server administrators can monitoring AMD hardware.

Background: AMD Secure Encrypted Virtualization with Secure Nested Paging (SEV-SNP) is designed to protect a guest VM’s data and memory from an untrusted or compromised host hypervisor. However, because RAPL is accessible by the host to track system energy, it can inadvertently expose the inner operations of the protected guest VM.

An attacker with root access to the host hypervisor can read RAPL Model-Specific Registers (MSRs) at high speeds. By analyzing these microjoule-level fluctuations, they can reconstruct what operations or data inputs are occurring inside the secure SEV-SNP virtual container. This mirrors the mechanics of the well-known “Platypus” side-channel attack.

The attack vector in the “Cohere+Reload” technique targets a spatial granularity of 2 kB blocks (coherence partitions) because of how the AMD EPYC hardware architecture manages coherence conflicts between encrypted and unencrypted memory states.

The 2 kB spatial granularity is not a random limitation; it is directly dictated by the structural boundary of AMD’s internal cache-coherence domains for secure memory. When the victim VM executes code or pulls data inside a specific 2 kB partition, it triggers a coherence conflict with the host hypervisor’s tracked lines. The Cohere+Reload attack works by having the attacker “Reload” a page and measure the execution timing. While the initial hardware conflict barrier occurs at the 2 kB block level, attackers can actually refine this spatial resolution down to 256 bytes by measuring the precise microsecond amplitude of the timing delay (which scales with the exact number of cache line evictions performed within that partition).  You can say that this 256-byte spatial resolution is precisely what allows an attacker to extract highly sensitive Confidential Virtual Machine (CVM) secrets. The 256-byte resolution directly aids the attacker in finding VM secrets because of how it aligns with common cryptographic vulnerabilities!

AMD-SB 3032 Overview:

The Core Threat: Attackers combine software-based power and cache side-channel techniques (like Cohere+Reload) to extract virtual machine secrets.

The Weakness:The reported technique relies heavily on hypervisor access to the RAPL (Running Average Power Limit) interface.

AMD’s Position:Fully malicious hypervisors fall outside the traditional SEV-ES threat model boundary.

The Mitigation:SEV-SNP mitigates this attack vector completely via a supported configuration option to restrict or disable hypervisor access to RAPL.

Official announcement: Please refer to link for details – https://www.amd.com/en/resources/product-security/bulletin/amd-sb-3032.html