Official Revision Date: 20-10-2025
Preface: A 3rd Gen AMD EPYC processor uses an integrated memory controller within its System on a Chip (SoC) to connect to DDR4 DRAM modules, rather than having a separate memory controller component. The memory controller is part of the I/O Die (IOD) which is connected to the Core Complex Dies (CCDs) via the Infinity Fabric. Each processor has up to eight memory channels, each capable of supporting up to two DIMM slots, for a maximum of 4TB of memory per socket.
Background: The secure memory area for the RMP (Reverse Map Table) on a 3rd Gen AMD EPYC processor is a protected region within the DDR4 DRAM modules themselves, managed by the processor’s security features. It is not located inside the SoC but is in a secure area of the system’s main RAM, making it part of the dedicated system memory rather than the processor’s on-chip memory.
In a 3rd Gen AMD EPYC processor, the secure memory area for the Reverse Map Table (RMP) is a protected region within the DDR4 DRAM modules themselves, not a separate “hidden area” on the SoC. The secure memory is managed by the processor’s security features, such as the AMD Secure Processor (ASP), to protect the RMP and prevent attacks that could manipulate it.
Vulnerability details: Researchers reported a cache-based side-channel that could allow an unprivileged user process on AMD Secure Encrypted Virtualization with Secure Nested Paging (SEV-SNP) systems to leak up to six bits of physical address information. The researchers also noted that this leakage does not have an immediate security impact.
AMD has determined that the leakage results from Reverse Map Table (RMP) entries being cached in the L1D and L2 caches. Given that at most six physical address bits are exposed, AMD concurs with the researchers that this leakage does not have an immediate security impact.
Ref: In the absence of an immediate fix from AMD, the only way to reduce the risk of cache-based side-channel attacks in SEV-SNP environments is to follow secure memory handling and system-level best practices.
Official announcement: Please see the link for details – https://www.amd.com/en/resources/product-security/bulletin/amd-sb-3036.html