Preface: The classic open-source code used to test Rowhammer (including verifying whether ECC can completely block it) primarily comes from Google’s Project Zero, CMU’s Safari Lab, and various chip security research teams.
Background: The real culprit is density: The underlying vulnerability of Rowhammer is caused by physical electrical leakage between adjacent memory rows. As manufacturing processes shrink to cram more data into smaller spaces, the physical distance between rows shrinks. This structural density lowers the number of activations needed to induce a bit-flip.
Above details captures the nuance of modern high-performance memory architecture, particularly concerning hardware like the NVIDIA H100.
Physical Threshold: It correctly identifies that the combination of high speed and high density creates shorter distances and faster access loops, physically lowering the threshold (the number of activations) required to trigger Rowhammer.
HBM3 ECC Limitations: The NVIDIA H100 uses advanced HBM3 (High Bandwidth Memory) which features robust, multi-tiered Error-Correcting Code (ECC) protections. Standard ECC is brilliant at catching and repairing single-bit errors or predictable double-bit errors.
Ref: In the NVIDIA H100, ECC (Error Correcting Code) protection is completely built-in across the entire memory hierarchy, operating seamlessly from the internal registers inside the shader cores all the way to the external high-bandwidth memory (HBM3).
How Shader Cores Interact with ECC Memory
When an H100 shader core processes a command (such as a matrix multiplication via Tensor Cores), the data undergoes a multi-layered verification cycle:
Shader Core / SM
1. Register File & L1 Cache > Protected by Internal SECDED ECC
2. Load/Store Instruction
3. L2 Cache > Checked & Corrected by Hardware Controller
4. Memory Controller
5. HBM3 VRAM > Sideband ECC Bits Checked
Remark: In the NVIDIA H100, ECC (Error Correcting Code) protection is completely built-in across the entire memory hierarchy, operating seamlessly from the internal registers inside the shader cores all the way to the external high-bandwidth memory (HBM3).
The shader cores—referred to by NVIDIA as Streaming Multiprocessors (SMs)—interact with ECC memory via dedicated hardware controllers without requiring any manual tracking or code implementation from developers.
Security Notice: NVIDIA has released updated guidance regarding Rowhammer mitigations for NVIDIA GPU and SoC products.
Solution: NVIDIA recommends a defense-in-depth posture, including enabling SYS-ECC and host IOMMU / DMA isolation.
Official announcement: Please refer to the link for details – https://nvidia.custhelp.com/app/answers/detail/a_id/5873