Publication date of this article: 12th June 2026
Preface: Because CVE-2025-54509 breaks that cryptographic isolation, it directly undermines the core trust assumption of AMD SEV-SNP because the hypervisor is the only entity that is supposed to be blocked by SEV-SNP, but is granted unauthorized access by this flaw.
Background: To understand why security advisories and researchers (such as the team behind the “Staleus” attack paper) specifically quote a “malicious hypervisor” even though a bare-metal host OS kernel has the exact same native authority.
But the crucial IOMMU only triggers when a peripheral device acts as the master and initiates a transaction over the PCIe/system bus.
How about MMU? MMU protects the system from unauthorized CPU access to memory and device registers.
The official vulnerability note described that an improper access control for register interface in the input-output memory management unit (IOMMU) could allow a privileged attacker. For example, AMD EPYC 9965 is explicitly built for High-Performance Computing (HPC) clusters. The AMD EPYC 9965 is engineered for high-density, multi-tenant computing environments, and it utilizes a massive PCIe 5.0 bus architecture. Processors, especially in heterogeneous systems (CPUs, GPUs, and accelerators) and embedded environments, use non-coherent memory access primarily to achieve higher performance, reduce power consumption, and minimize hardware complexity.
Ref:Non-coherent memory access occurs when multiple agents (like a CPU and a DMA controller) access the same memory location, but their local caches are not automatically synchronized, leading to potential data inconsistencies. It requires software to explicitly manage cache maintenance (flushing or invalidating) to ensure data integrity.
Vulnerability details:
Primary Target Generation – 5th Gen AMD EPYC (Turin) platforms.
Exploitation Core Flaw – Lack of access control rules governing IOMMU memory-coherency configuration registers.
Attack Execution Mechanics – Host flips a bit forcing the AMD Secure Processor (ASP) to use non-coherent lines, pulling stale table data directly from DRAM.
Security Impact Profile – Complete collapse of Reverse Map Table (RMP) validation, causing cross-domain integrity failures.
Primary Remediation – SB-3039 PI microcode patch + operating system level MMIO mapping restrictions.
Official announcement: Please refer to the link for details – https://nvd.nist.gov/vuln/detail/CVE-2025-54509